The invention relates generally to plasma etching. In particular, the invention relates to a method of etching oxide and other dielectric layers, such as nitride layers, in semiconductor integrated circuits.
Modern silicon integrated circuits contain millions to tens of millions of interconnected semiconductor devices. Such a high level of integration has been achieved, at least in part, by decreasing the minimum feature sizes and by providing multiple wiring layers of horizontally extending metallization lines. Dielectric layers separate the horizontal parts of the wiring layers, which are selectively connected with small-area vertical metallization interconnects. After holes for such vertical interconnects are etched in the dielectric layer, they are filled with a metallization, such as tungsten, thereby forming the vertical connection. Often for upper inter-metal connections, aluminum or copper is simultaneously filled in the hole and also forms the horizontal interconnections above the dielectric layer. In the case of a dielectric layer separating a silicon substrate having active semiconductor areas with a first-level metallization layer, the dielectric is called a first-level dielectric (FLD) and the vertical interconnect is called a contact. When the dielectric separates two metallization layers, the dielectric is called an inter-metal dielectric (IMD) and the vertical interconnect is called a via. This invention will be primarily described with respect to the formation of the contact holes by dry plasma etching, but many of the features of the invention apply as well to vias and to other more complex structures.
The dielectric layers have conventionally been composed of a silica-based oxide, whether it is silicon dioxide grown in a plasma CVD process using TEOS or other precursor, or a borophospho silicate glass (BPSG) deposited using sub-atmospheric CVD (SACVD), or other dielectric materials. More recently, low-k dielectric materials have been developed for use as inter-level dielectrics. One is a fluorosilicate glass (FSG) having a fluorine concentration of 5 to 12 atomic %. The lower dielectric constants of these materials offer the possibility of reduced capacitive coupling between horizontally or vertically adjacent lines, thus reducing cross talk, power consumption, and signal rise time. Low-k dielectrics have been proposed having varying compositions, some silicon-based, and other carbon-based. One such class of low-k dielectrics involves an organo-silicate glass, which will be described in some more detail below.
As will be explained below, etching of the via or contact holes in advanced structures presents increasing difficulty because of the decreasing widths and increasing aspect ratios of the holes. Furthermore, the structures are becoming more complex to allow the formation of dense, complicated circuits with a minimum number of steps. Some of these structures have imposed difficult requirements upon the etching process.
One such advanced structure is a multi-level direct contact (DC), illustrated in cross section in FIG. 2, which is used in most modem designs for dynamic random access memories (DRAMs). A semiconducting silicon substrate 10, as illustrated in FIG. 1, has formed in its surface unillustrated doped regions and other structure for use as active devices in the memory circuit. A polysilicon line 12 is deposited over the silicon substrate 10 to thickness of about 250 nm and etched to a width in the range of 0.1 to 0.25 xcexcm to act as a transistor gate. A silicon nitride layer is deposited approximately conformally over the polysilicon line 12 as a top portion 14 over the polysilicon line and possibly on the sides as spacers 15. The nitride acts as a either a spacer or as an etch mask for patterning polysilicon. Nitride is a somewhat generic term for compositions close to Si3N4, but a wider compositional range is given by SiNx with 1xe2x89xa6xxe2x89xa61.5.
The first-level dielectric layer is deposited in two parts. The lower part is a BPSG layer 16 of about 950 nm of borophospho silicate glass (BPSG), which can be deposited by low-pressure CVD (LPCVD) or atomospheric pressure CVD (APCVD). The upper part is a TEOS layer 18 of about 100 nm of TEOS oxide, which can be deposited in a low-temperature process by plasma-enhanced chemical vapor deposition (PECVD) using tetraethyl orthosilicate (TEOS) as the precursor gas. Both these materials are composed of silicon dioxide but with somewhat different compositions and additives, The relatively thin TEOS layer 18 is included as an adhesion layer as well as a diffusion barrier. An oxide layer is one having a composition generally corresponding to silica or SiO2 but it also includes doped silica such as borophosphosilicate glass (BPSG) and other spin-on glasses (SOGs) and fluorosilicate glass (FSG) among other silica-based low-k dielectrics.
A photoresist layer 18 is deposited on the first level dielectric layers 16, 18 to a thickness of about 550 nm and is photographically patterned with pairs of masking apertures 22, 24. Greater thicknesses of photoresist would degrade the photographic patterning of such small apertures so that a minimum level of selectivity to photoresist is required during the oxide and nitride etching. The critical dimension of these structures is 0.20 to 0.35 xcexcm or less so that a deep ultra-violet (DUV) photoresist is needed for patterning with the shorter-wavelength DUV light. DUV photoresist sometimes presents a problem when it is applied over other unillustrated surface structure having deep, narrow gaps because it may need to be reflowed, that is, heated after it is spun on, so that it fills the gaps. Reflowed photoresist tends to be patterned with necked apertures that flare outwardly both at the bottom but more particularly at the top. The top flaring can be characterized as facets 26 formed on the top corners of the photoresist. During most conventional etching processes, the photoresist is etched most strongly at its corners so that photoresist facets form and grow even when they are not initially present. If the facets reach the layers being etched, the critical dimension is lost. Photoresist faceting is considered the most likely cause of loss of critical dimension when very narrow holes are being etched. Reflowed DUV photoresist presents an even greater challenge because of the necking incurred in developing of the photoresist even before the etching.
The patterned wafer is then etched to form, as illustrated in the cross-sectional view of FIG. 2, a poly contact hole 10 and a silicon contact hole 32 of two different depths. The etching process must reach through the two different types of oxide 16, 18, also etch through the nitride 14 but stop on the polysilicon 12 and silicon 10. The requirement of selectivity to silicon (including polysilicon), however achieved, is intensified because a common etching process is etching through two substantially different thicknesses of oxide. Furthermore, the holes being etched have high aspect ratios, more than 4:1 for 0.3 xcexcm holes and 10:1 for 0.13 xcexcm holes being contemplated.
The process must also be sufficiently selective to the photoresist. Photoresist selectivity has always been a concern in oxide etching, but nitride selectivity has usually been a greater concern. However, it appears that for very narrow structures, the photoresist selectivity will be the most difficult requirement imposed on the oxide etch. A further problem is that under some conditions vertically extending striations form in the photoresist sidewalls and these striations can propagate into the underlying oxide as the etching continues. A striated contact hole of high aspect ratio is very difficult to fill with metallization.
A multi-step process is possible in which the different oxide and nitride levels are sequentially etched. However, in the interest of simplicity and throughput, it is preferred if possible to perform a one-step etch or at least one not involving a great change in processing conditions through the etch step.
Recent developments have shown that a fluorocarbon plasma can etch holes in oxide with aspect ratios up to about 5:1 with very high selectivity to nitride if a heavy hydrogen-free fluorocarbon is used in combination with a larger fraction of a carrier gas. The fluorocarbon should have a low-F/C ratio, such as hexafluorobutadiene (C4F6). Argon is the conventional carrier gas for plasma etching, but even better nitride selectivity without etch stop is obtained if xenon is used as the carrier gas in combination with the heavy fluorocarbons.
Other fluorocarbon etching recipes are also popular, including ones based on carbon tetrafluoride (CF4) and octafluorocyclobutane (C4F8). If possible, it would be desirable to develop a suitable recipe relying on these more conventional fluorocarbon etchants.
It is desirable that the process be practiced on a conventional capacitively coupled etch reactors, often referred to as diode reactors, and preferably including magnetic enhancement of the plasma. An example of such a magnetically enhanced reactive ion etch (MERIE) reactor 40 is schematically illustrated in FIG. 3. Similar reactors are available from Applied Materials of Santa Clara, Calif. The reactor 40 includes a grounded vacuum chamber 42, perhaps including liners to protect the walls. A wafer 44 is inserted into the chamber 42 through a slit valve opening 46 and placed on a cathode pedestal 48 with an electrostatic chuck 50 selectively clamping the wafer. The chuck powering is not illustrated. Unillustrated fluid cooling channels through the pedestal 48 maintain the pedestal at reduced temperatures. A thermal transfer gas such as helium is supplied to unillustrated grooves in the upper surface of the pedestal 48. The thermal transfer increases the efficiency of thermal coupling between the pedestal 48 and the wafer 44, which is held against the pedestal 48 by the electrostatic chuck 50 or an alternatively used peripheral wafer clamp.
An RF power supply 52, preferably operating at 13.56 MHz, is connected to the cathode pedestal 48 and provides the only significant power for generating the plasma while also controlling the DC self-bias. Magnetic coils 54 powered by unillustrated current supplies surround the chamber 42 and generate a slowly rotating (on the order of seconds and almost always greater than 10 ms), horizontal, essentially DC magnetic field in order to increase the density of the plasma. A vacuum pump system 56 pumps the chamber 42 through an adjustable throttle valve 58. Shields 60, 62 not only protect the chamber 42 and pedestal 48 but also define a baffle 64 and a pumping channel 66 connected to the throttle valve 58.
Processing gases are supplied from gas sources 68, 70, 72, 74 through respective mass flow controllers 76, 78, 80, 82 to a quartz gas distribution plate 84 positioned in the roof of the chamber 42 overlying the wafer 44 and separated from it across a processing region 86. The composition of the etching gas is a subject matter of one aspect of the present invention. The distribution plate 84 includes a manifold 88 receiving the processing gas and communicating with the processing region 86 through a showerhead having a large number of distributed apertures 90 so as to inject a more uniform flow of processing gas into the processing region 86.
The invention includes a plasma process for etching oxide and nitride in a one-step process using a principal fluorocarbon etching gas, oxygen, and added polymerizing components of difluoromethane and carbon monoxide, thereby achieving high selectivity to silicon and photoresist.
The preferred fluorocarbons have F/C ratios of no more than 2, and more preferably no more than 1.6. The most preferred fluorocarbon is hexafluorobutadiene (C4F6) although good results are also obtained with octafluorocyclobutane (C4F8). However, carbon tetrafluoride (CF4) is also effective.
The fluorocarbon, oxygen, and difluoromethane are present in approximately equal amounts. The carbon monoxide is present in a much larger amounts.
The process is preferably performed at high chamber pressures and high magnetic field.
The chemistry is also effective in etching organo-silicate glasses, and in particular to etch such glasses selectively to silicon carbide (SiC).